1. Field of the Invention:
The present invention relates to a memory integrated circuit and, more particularly, to a CMOS type memory integrated circuit having data-retention function or stand-by function that holds stored data by a low power voltage supplied from a backup battery or the like.
2. Description of the Related Art:
A static semiconductor memory circuit, e.g. a CMOS static random access memory circuit (hereinafter abbreviated as CMOS SRAM), is frequently operated as a nonvolatile memory by holding internal data by means of a backup power source such as a battery, because a leak current in each input stage of an external signal controlled by a chip select signal (hereinafter abbreviated as CS signal) is virtually zero in a standby state wherein the CS signal is at a high, inactive level and, accordingly, a consumed current is very small only with a little holding current required for memory cells. A low supply voltage of about 2 V may be used for data holding.
An operation for holding internal data is conducted generally in the CMOS SRAM by raising the CS signal to a high inactive level such as a supply voltage V.sub.CC level. Then, an internal control signal outputted from an input inverter receiving the CS signal turns high. Thereby transistors provided in input stages receiving externally supplied signals other than the CS input inverter are controlled so that each input stage circuit is put in a non-active state, and the internal data are held by supplying a holding current for the memory cells from the backup power source.
The CMOS SRAM of this kind is usually provided with a supply voltage detecting circuit which detects that the value of the supply voltage falls below a reference voltage level. When the supply voltage falls below the reference voltage level, the input stages are also automatically put in the non-active state.
However, in the stand-by mode of the SRAM, if induced noise or the like is applied to the CS signal, the SRAM is erroneously put into an active state temporarily. In this instance, if an input terminal of a write control signal is at an active level (in a write mode), it sometimes happens that data at a data input terminal are erroneously written into the SRAM. Therefore, it is necessary to take, as a preventive measure, a means to keep the voltage level at the input terminal of the write signal at an inactive level such as a supply voltage V.sub.CC by means of an external resistance, or the like.
Moreover, if noise or the like is applied to the power supply line to temporarily lower the supply voltage at the supply line below the reference voltage during the active state of the SRAM, the input stages are erroneously put in the non-active state so that data stored in the memory cells are destroyed.